Saturday, 10 March 2012

XAUI

XAUI is a accepted for extending the XGMII (10 Gigabit Media Independent Interface) amid the MAC and PHY band of 10 Gigabit Ethernet (10GbE). XAUI is arresting "zowie", a chain of the Roman character X, acceptation ten, and the brand of "Attachment Unit Interface

".

The XGMII Extender, which is composed of an XGXS at the MAC end, an XGXS at the PHY end and a XAUI amid them, is to extend the operational ambit of the XGMII and to abate the cardinal of interface signals. Applications accommodate extending the concrete break accessible amid MAC and PHY apparatus in a 10 Gigabit Ethernet arrangement broadcast beyond a ambit board.

Operation

XAUI has the afterward characteristics:

Simple arresting mapping to the XGMII

Independent address and accept abstracts paths

Four lanes carrying the XGMII 32-bit abstracts and control

Differential signaling with low voltage beat (1600 mV(p-p))

Self-timed interface allows jitter ascendancy to the PCS

Shared technology with added 10 Gbit/s interfaces

Shared functionality with added 10 Gbit/s Ethernet blocks

Utilization of 8b/10b encoding

The afterward is a account of the above concepts of XGXS and XAUI:

The alternative XGMII Extender can be amid amid the Reconciliation Sublayer and the PHY (physical layer) to clearly extend the concrete ability of the XGMII and abate the interface pin calculation from 72 to 16.

The XGMII is organized into four lanes with anniversary lane carrying a abstracts octet or ascendancy appearance on anniversary bend of the associated clock. The antecedent XGXS converts bytes on an XGMII lane into a cocky clocked, serial, 8b/10b encoded abstracts stream. Anniversary of the four XGMII lanes is transmitted beyond one of the four XAUI lanes.

The antecedent XGXS converts XGMII Idle ascendancy characters (interframe) into an 8b/10b cipher sequence. The destination XGXS recovers alarm and abstracts from anniversary XAUI lane and deskews the four XAUI lanes into the single-clock XGMII.

The destination XGXS adds to or deletes from the interframe as bare for alarm amount alterity advantage above-mentioned to converting the interframe cipher arrangement aback into XGMII Idle ascendancy characters.

The XGXS uses the aforementioned cipher and coding rules as the 10GBASE-X PCS and PMA defined in Clause 48 of the IEEE 802.3 Specification.

Anniversary of the 4 Accept and Address lanes operates at a amount of 3.125 Gbit/s.

Capabilities accept been congenital into XAUI to affected the inter-lane signal-skewing problems application a blazon of automated de-skewing. Signals can be launched at the transmitter end of a XAUI band after absolutely analogous the acquisition of the four lanes, and the signals will be automatically de-skewed at the receiver.1

Intended Use

The accomplishing of XAUI as an alternative XGMII Extender is primarily advised as a chip-to-chip (integrated ambit to chip circuit) interface implemented with traces on a printed ambit board. Where the XGMII is electrically bound to distances of about 7 cm, the XGMII Extender allows distances up to about 50 cm.

Rate of operation

The XGMII Extender supports the 10 Gbit/s abstracts amount of the XGMII. The 10 Gbit/s MAC abstracts beck is adapted into four lanes at the XGMII (by the Reconciliation Sublayer for address or the PHY for receive). The byte beck of anniversary lane is 8b/10b encoded by the XGXS for manual beyond the XAUI at a nominal amount of 3.125 GBaud. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may accomplish on absolute clocks.

Allocation of functions

The XGMII Extender is cellophane to the Reconciliation Sublayer and PHY device, and operates symmetrically with agnate functions on the DTE address and accept abstracts paths. The XGMII Extender is logically composed of two XGXSs commutual with a XAUI abstracts aisle in anniversary direction. One XGXS acts as the antecedent to the XAUI abstracts aisle in the DTE address aisle and as the destination in the accept path. The added XGXS is the destination in the address aisle and antecedent in the accept path. Anniversary XAUI abstracts aisle is composed of four consecutive lanes. All blueprint for the XGMII Extender are accounting bold about-face from XGMII to XAUI and aback to XGMII, but added techniques may be active provided that the aftereffect is that the XGMII Extender operates as if all defined conversions had been made. One archetype of this is the use of the alternative XAUI with the 10GBASE-LX4 8b/10b PHY, area the XGXS interfacing to the Reconciliation Sublayer provides the PCS and PMA functionality appropriate by the PHY. An XGXS band is not appropriate at the PHY end of the XAUI in this case. However, agency may still be appropriate to abolish jitter alien on the XAUI in adjustment to accommodated PHY jitter requirements.