XAUI has the afterward characteristics:
Simple arresting mapping to the XGMII
Independent address and accept abstracts paths
Four lanes carrying the XGMII 32-bit abstracts and control
Differential signaling with low voltage beat (1600 mV(p-p))
Self-timed interface allows jitter ascendancy to the PCS
Shared technology with added 10 Gbit/s interfaces
Shared functionality with added 10 Gbit/s Ethernet blocks
Utilization of 8b/10b encoding
The afterward is a account of the above concepts of XGXS and XAUI:
The alternative XGMII Extender can be amid amid the Reconciliation Sublayer and the PHY (physical layer) to clearly extend the concrete ability of the XGMII and abate the interface pin calculation from 72 to 16.
The XGMII is organized into four lanes with anniversary lane carrying a abstracts octet or ascendancy appearance on anniversary bend of the associated clock. The antecedent XGXS converts bytes on an XGMII lane into a cocky clocked, serial, 8b/10b encoded abstracts stream. Anniversary of the four XGMII lanes is transmitted beyond one of the four XAUI lanes.
The antecedent XGXS converts XGMII Idle ascendancy characters (interframe) into an 8b/10b cipher sequence. The destination XGXS recovers alarm and abstracts from anniversary XAUI lane and deskews the four XAUI lanes into the single-clock XGMII.
The destination XGXS adds to or deletes from the interframe as bare for alarm amount alterity advantage above-mentioned to converting the interframe cipher arrangement aback into XGMII Idle ascendancy characters.
The XGXS uses the aforementioned cipher and coding rules as the 10GBASE-X PCS and PMA defined in Clause 48 of the IEEE 802.3 Specification.
Anniversary of the 4 Accept and Address lanes operates at a amount of 3.125 Gbit/s.
Capabilities accept been congenital into XAUI to affected the inter-lane signal-skewing problems application a blazon of automated de-skewing. Signals can be launched at the transmitter end of a XAUI band after absolutely analogous the acquisition of the four lanes, and the signals will be automatically de-skewed at the receiver.1
Simple arresting mapping to the XGMII
Independent address and accept abstracts paths
Four lanes carrying the XGMII 32-bit abstracts and control
Differential signaling with low voltage beat (1600 mV(p-p))
Self-timed interface allows jitter ascendancy to the PCS
Shared technology with added 10 Gbit/s interfaces
Shared functionality with added 10 Gbit/s Ethernet blocks
Utilization of 8b/10b encoding
The afterward is a account of the above concepts of XGXS and XAUI:
The alternative XGMII Extender can be amid amid the Reconciliation Sublayer and the PHY (physical layer) to clearly extend the concrete ability of the XGMII and abate the interface pin calculation from 72 to 16.
The XGMII is organized into four lanes with anniversary lane carrying a abstracts octet or ascendancy appearance on anniversary bend of the associated clock. The antecedent XGXS converts bytes on an XGMII lane into a cocky clocked, serial, 8b/10b encoded abstracts stream. Anniversary of the four XGMII lanes is transmitted beyond one of the four XAUI lanes.
The antecedent XGXS converts XGMII Idle ascendancy characters (interframe) into an 8b/10b cipher sequence. The destination XGXS recovers alarm and abstracts from anniversary XAUI lane and deskews the four XAUI lanes into the single-clock XGMII.
The destination XGXS adds to or deletes from the interframe as bare for alarm amount alterity advantage above-mentioned to converting the interframe cipher arrangement aback into XGMII Idle ascendancy characters.
The XGXS uses the aforementioned cipher and coding rules as the 10GBASE-X PCS and PMA defined in Clause 48 of the IEEE 802.3 Specification.
Anniversary of the 4 Accept and Address lanes operates at a amount of 3.125 Gbit/s.
Capabilities accept been congenital into XAUI to affected the inter-lane signal-skewing problems application a blazon of automated de-skewing. Signals can be launched at the transmitter end of a XAUI band after absolutely analogous the acquisition of the four lanes, and the signals will be automatically de-skewed at the receiver.1
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